1. Technical Field
The present invention relates to a semiconductor memory device, and in particular, to a semiconductor memory device at which gate arrays are also provided (a gate arrays mixed-loaded semiconductor memory) and that is realized by three layers of wiring.
2. Related Art
Conventionally, when mixed-loading gate arrays at a semiconductor memory device of three layers of wiring (e.g., a first layer of vertical wiring, a second layer of lateral wiring, and a third layer of vertical wiring), there is generally used a method that disposes gate array regions at a position at which all of the wiring layers can be utilized, and circuit wiring is carried out by using only that region.
From Japanese Patent Application Laid-Open (JP-A) No. 2008-71865, there is known a method that disposes basic cells below the power supply wiring so as to effectively utilize the region below the power supply wiring. This JP-A No. 2008-71865 discloses a layout method in which, by disposing the basic cells below the power supply wiring at the time of repairing circuits, the circuits can be changed without changing the chip size or the lower layer portion.
There is proposed a device (see JP-A No. 2008-71865) that, in order to shorten overall processing time, carries out regular processings by hardware and carries out irregular processings by software.
However, in the method of disposing the gate array regions at a position at which all of the wiring layers can be utilized, the gate array regions must be enlarged in accordance with the circuit scale, which leads to an increase in the chip surface area.
Further, in the technique of JP-A No. 2008-71865, the basic cells are disposed beneath the power supply wiring, and the region below the power supply wiring is utilized effectively. However, the basic cells that are disposed here are limited to dummy basic cells that are used in circuit repair from the contact hole process and thereafter. Further, when the basic cells are disposed beneath the power supply wiring and are used as the gate array regions, at this region, one layer among the three wiring layers is occupied by the power supply wiring, and therefore, there are two wiring layers that can be used for the wiring of the circuits. Accordingly, violations (the impossibility of circuit wiring) due to congestion of wires, and the like, arise, and this region cannot be used as usual gate array regions.